668 lines
12 KiB
ArmAsm
668 lines
12 KiB
ArmAsm
# This Source Code Form is subject to the terms of the Mozilla Public
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# License, v. 2.0. If a copy of the MPL was not distributed with this
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# file, You can obtain one at http://mozilla.org/MPL/2.0/.
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# vs0 - vs15 : buffer for xor
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# vs32 - vs47 (v0 - v15) : 4 "converted" states
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# vs48 - vs51 (v16 - v19) : original state
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# vs52 - vs55 (v20 - v23) : "converted" constants
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# vs56 (v24) : "converted" counter
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# vs57 (v25) : increment for "converted" counter
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# vs60 - vs63 (v28 - v31) : constants for rotate left or vpermxor
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#define r0 0
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#define sp 1
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#define r2 2
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#define rSIZE 3
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#define rDST 4
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#define rSRC 5
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#define rKEY 6
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#define rNONCE 7
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#define rCNTR 8
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#define r9 9
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#define r10 10
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#define r11 11
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#define r12 12
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#define r13 13
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#define r14 14
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#define r15 15
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#define r16 16
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#define r17 17
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#define r18 18
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#define r19 19
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#define r20 20
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#define r21 21
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#define r22 22
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#define r23 23
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#define r24 24
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#define r25 25
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#define r26 26
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#define r27 27
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#define r28 28
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#define r29 29
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#define r30 30
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#define r31 31
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#define v0 0
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#define v1 1
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#define v2 2
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#define v3 3
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#define v4 4
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#define v5 5
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#define v6 6
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#define v7 7
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#define v8 8
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#define v9 9
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#define v10 10
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#define v11 11
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#define v12 12
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#define v13 13
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#define v14 14
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#define v15 15
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#define v16 16
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#define v17 17
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#define v18 18
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#define v19 19
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#define v20 20
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#define v21 21
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#define v22 22
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#define v23 23
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#define v24 24
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#define v25 25
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#define v26 26
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#define v27 27
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#define v28 28
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#define v29 29
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#define v30 30
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#define v31 31
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#define vs0 0
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#define vs1 1
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#define vs2 2
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#define vs3 3
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#define vs4 4
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#define vs5 5
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#define vs6 6
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#define vs7 7
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#define vs8 8
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#define vs9 9
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#define vs10 10
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#define vs11 11
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#define vs12 12
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#define vs13 13
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#define vs14 14
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#define vs15 15
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#define vs16 16
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#define vs17 17
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#define vs18 18
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#define vs19 19
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#define vs20 20
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#define vs21 21
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#define vs22 22
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#define vs23 23
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#define vs24 24
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#define vs25 25
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#define vs26 26
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#define vs27 27
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#define vs28 28
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#define vs29 29
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#define vs30 30
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#define vs31 31
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#define vs32 32
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#define vs33 33
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#define vs34 34
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#define vs35 35
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#define vs36 36
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#define vs37 37
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#define vs38 38
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#define vs39 39
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#define vs40 40
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#define vs41 41
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#define vs42 42
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#define vs43 43
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#define vs44 44
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#define vs45 45
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#define vs46 46
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#define vs47 47
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#define vs48 48
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#define vs49 49
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#define vs50 50
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#define vs51 51
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#define vs52 52
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#define vs53 53
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#define vs54 54
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#define vs55 55
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#define vs56 56
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#define vs57 57
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#define vs58 58
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#define vs59 59
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#define vs60 60
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#define vs61 61
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#define vs62 62
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#define vs63 63
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.abiversion 2
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.section ".data"
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.align 5
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lblock: .skip 256
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cnts0: .long 0x61707865, 0x3320646e, 0x79622d32, 0x6b206574
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cnts1: .long 0x61707865, 0x61707865, 0x61707865, 0x61707865
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cnts2: .long 0x3320646e, 0x3320646e, 0x3320646e, 0x3320646e
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cnts3: .long 0x79622d32, 0x79622d32, 0x79622d32, 0x79622d32
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cnts4: .long 0x6b206574, 0x6b206574, 0x6b206574, 0x6b206574
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st4: .long 0, 0, 0, 0
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cntr: .long 0, 0, 0, 0
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incr: .long 4, 4, 4, 4
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rotl1: .long 0x22330011, 0x66774455, 0xAABB8899, 0xEEFFCCDD
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rotl2: .long 12, 12, 12, 12
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rotl3: .long 0x11223300, 0x55667744, 0x99AABB88, 0xDDEEFFCC
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rotl4: .long 7, 7, 7, 7
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.section ".text"
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.align 5
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.globl chacha20vsx
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.type chacha20vsx, @function
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chacha20vsx:
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# prologue
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addis 2, r12, .TOC.-chacha20vsx@ha
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addi 2, 2, .TOC.-chacha20vsx@l
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.localentry chacha20vsx, .-chacha20vsx
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std r14, -8(sp)
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std r15, -16(sp)
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std r16, -24(sp)
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std r17, -32(sp)
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std r18, -40(sp)
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std r19, -48(sp)
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std r20, -56(sp)
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std r21, -64(sp)
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std r22, -72(sp)
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std r23, -80(sp)
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std r24, -88(sp)
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std r25, -96(sp)
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std r26, -104(sp)
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std r27, -112(sp)
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std r28, -120(sp)
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std r29, -128(sp)
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std r30, -136(sp)
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std r31, -144(sp)
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addi r14, sp, -160
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li r16, -16
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li r17, -32
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li r18, -48
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li r19, -64
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li r20, -80
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li r21, -96
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li r22, -112
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li r23, -128
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li r24, -144
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li r25, -160
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li r26, -176
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li r27, -192
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li r28, -208
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# save f14, f15
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stxvw4x vs14, 0, r14
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stxvw4x vs15, r16, r14
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# save v20 - v31
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stxvw4x vs52, r17, r14
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stxvw4x vs53, r18, r14
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stxvw4x vs54, r19, r14
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stxvw4x vs55, r20, r14
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stxvw4x vs56, r21, r14
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stxvw4x vs57, r22, r14
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stxvw4x vs58, r23, r14
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stxvw4x vs59, r24, r14
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stxvw4x vs60, r25, r14
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stxvw4x vs61, r26, r14
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stxvw4x vs62, r27, r14
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stxvw4x vs63, r28, r14
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# offset in src/dst
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li r17, 16
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li r18, 32
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li r19, 48
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li r20, 64
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li r21, 80
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li r22, 96
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li r23, 112
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li r24, 128
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li r25, 144
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li r26, 160
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li r27, 176
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li r28, 192
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li r29, 208
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li r30, 224
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li r31, 240
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# load const's address
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addis r14, 2, cnts0@toc@ha
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addi r14, r14, cnts0@toc@l
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# save nonce to st4
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lwz r15, 0(rNONCE)
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stw r15, 84(r14)
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lwz r15, 4(rNONCE)
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stw r15, 88(r14)
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lwz r15, 8(rNONCE)
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stw r15, 92(r14)
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# load state to vectors
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lxvw4x vs48, 0, r14
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lxvw4x vs49, 0, rKEY
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lxvw4x vs50, r17, rKEY
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lxvw4x vs51, r21, r14
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# load consts for x4 rounds
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lxvw4x vs52, r17, r14
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lxvw4x vs53, r18, r14
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lxvw4x vs54, r19, r14
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lxvw4x vs55, r20, r14
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# counter
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stw rCNTR, 96(r14)
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addi rCNTR, rCNTR, 1
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stw rCNTR, 100(r14)
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addi rCNTR, rCNTR, 1
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stw rCNTR, 104(r14)
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addi rCNTR, rCNTR, 1
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stw rCNTR, 108(r14)
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lxvw4x vs56, r22, r14
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# load increment
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lxvw4x vs57, r23, r14
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# load rotl to vectors
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lxvw4x vs60, r24, r14
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lxvw4x vs61, r25, r14
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lxvw4x vs62, r26, r14
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lxvw4x vs63, r27, r14
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# counter for loop = size/256
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li r15, 256
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divdu. r16, rSIZE, r15
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beq lastblock
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mtctr r16
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mainloop:
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# init 16 vectors (4 states x4)
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vor v0, v20, v20
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vor v1, v21, v21
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vor v2, v22, v22
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vor v3, v23, v23
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vspltw v4, v17, v0
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vspltw v5, v17, v1
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vspltw v6, v17, v2
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vspltw v7, v17, v3
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vspltw v8, v18, v0
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vspltw v9, v18, v1
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vspltw v10, v18, v2
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vspltw v11, v18, v3
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vor v12, v24, v24
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vspltw v13, v19, v1
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vspltw v14, v19, v2
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vspltw v15, v19, v3
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.macro _plus a b_y b_x
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vadduwm \a, \a, \b_y*4+(\b_x)%4
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vadduwm \a+1, \a+1, \b_y*4+(\b_x+1)%4
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vadduwm \a+2, \a+2, \b_y*4+(\b_x+2)%4
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vadduwm \a+3, \a+3, \b_y*4+(\b_x+3)%4
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.endm
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.macro _xor a b_y b_x
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vxor \a, \a, \b_y*4+(\b_x)%4
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vxor \a+1, \a+1, \b_y*4+(\b_x+1)%4
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vxor \a+2, \a+2, \b_y*4+(\b_x+2)%4
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vxor \a+3, \a+3, \b_y*4+(\b_x+3)%4
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.endm
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.macro _rotl a b
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vrlw \a, \a, \b
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vrlw \a+1, \a+1, \b
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vrlw \a+2, \a+2, \b
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vrlw \a+3, \a+3, \b
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.endm
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.macro _pxor a b_y b_x c
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vpermxor \a, \a, \b_y*4+(\b_x)%4, \c
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vpermxor \a+1, \a+1, \b_y*4+(\b_x+1)%4, \c
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vpermxor \a+2, \a+2, \b_y*4+(\b_x+2)%4, \c
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vpermxor \a+3, \a+3, \b_y*4+(\b_x+3)%4, \c
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.endm
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# 00 01 02 03
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# 04 05 06 07
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# 08 09 10 11
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# 12 13 14 15
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.macro doubleround
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# column round
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_plus v0, v1, v0 # a+=b
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_pxor v12, v0, v0, v28 # d^=a; d<<<=16
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_plus v8, v3, v0 # c+=d
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_xor v4, v2, v0 # b^=c
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_rotl v4, v29 # b<<<=12
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_plus v0, v1, v0 # a+=b
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_pxor v12, v0, v0, v30 # d^=a; d<<<=8
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_plus v8, v3, v0 # c+=d
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_xor v4, v2, v0 # b^=c
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_rotl v4, v31 # b<<<=7
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# diagonal round
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_plus v0, v1, v1 # a+=b
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_pxor v12, v0, v1, v28 # d^=a; d<<<=16
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_plus v8, v3, v1 # c+=d
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_xor v4, v2, v1 # b^=c
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_rotl v4, v29 # b<<<=12
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_plus v0, v1, v1 # a+=b
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_pxor v12, v0, v1, v30 # d^=a; d<<<=8
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_plus v8, v3, v1 # c+=d
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_xor v4, v2, v1 # b^=c
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_rotl v4, v31 # b<<<=7
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.endm
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doubleround # 1
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doubleround # 2
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doubleround # 3
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doubleround # 4
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doubleround # 5
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doubleround # 6
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doubleround # 7
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doubleround # 8
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doubleround # 9
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doubleround # 10
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# counter += original counter
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vadduwm v12, v12, v24
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.macro convert a
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vmrgew 26, 0+\a, 1+\a
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vmrgew 27, 2+\a, 3+\a
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vmrgow 0+\a, 0+\a, 1+\a
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vmrgow 2+\a, 2+\a, 3+\a
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xxmrghd 33+\a, 32+\a, 34+\a
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xxmrgld 35+\a, 32+\a, 34+\a
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xxmrghd 32+\a, 58, 59
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xxmrgld 34+\a, 58, 59
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.endm
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convert 0
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convert 4
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convert 8
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convert 12
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.macro addition a
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vadduwm 0+\a, 0+\a, 16
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vadduwm 4+\a, 4+\a, 17
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vadduwm 8+\a, 8+\a, 18
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vadduwm 12+\a, 12+\a, 19
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.endm
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addition 0
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addition 1
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addition 2
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addition 3
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# load text/cipher
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lxvw4x vs0, 0, rSRC
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lxvw4x vs1, r17, rSRC
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lxvw4x vs2, r18, rSRC
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lxvw4x vs3, r19, rSRC
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lxvw4x vs4, r20, rSRC
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lxvw4x vs5, r21, rSRC
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lxvw4x vs6, r22, rSRC
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lxvw4x vs7, r23, rSRC
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lxvw4x vs8, r24, rSRC
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lxvw4x vs9, r25, rSRC
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lxvw4x vs10, r26, rSRC
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lxvw4x vs11, r27, rSRC
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lxvw4x vs12, r28, rSRC
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lxvw4x vs13, r29, rSRC
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lxvw4x vs14, r30, rSRC
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lxvw4x vs15, r31, rSRC
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# xor (encrypt/decrypt)
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xxlxor vs0, vs0, vs32
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xxlxor vs1, vs1, vs36
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xxlxor vs2, vs2, vs40
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xxlxor vs3, vs3, vs44
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xxlxor vs4, vs4, vs33
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xxlxor vs5, vs5, vs37
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xxlxor vs6, vs6, vs41
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xxlxor vs7, vs7, vs45
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xxlxor vs8, vs8, vs34
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xxlxor vs9, vs9, vs38
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xxlxor vs10, vs10, vs42
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xxlxor vs11, vs11, vs46
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xxlxor vs12, vs12, vs35
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xxlxor vs13, vs13, vs39
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xxlxor vs14, vs14, vs43
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xxlxor vs15, vs15, vs47
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# store cipher/text
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stxvw4x vs0, 0, rDST
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stxvw4x vs1, r17, rDST
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stxvw4x vs2, r18, rDST
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stxvw4x vs3, r19, rDST
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stxvw4x vs4, r20, rDST
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stxvw4x vs5, r21, rDST
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stxvw4x vs6, r22, rDST
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stxvw4x vs7, r23, rDST
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stxvw4x vs8, r24, rDST
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stxvw4x vs9, r25, rDST
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stxvw4x vs10, r26, rDST
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stxvw4x vs11, r27, rDST
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stxvw4x vs12, r28, rDST
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stxvw4x vs13, r29, rDST
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stxvw4x vs14, r30, rDST
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stxvw4x vs15, r31, rDST
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# src/dst increment
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addi rSRC, rSRC, 256
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addi rDST, rDST, 256
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# counter increment
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vadduwm v24, v24, v25
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bdnz mainloop
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lastblock:
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# reminder
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mulld r16, r16, r15
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subf. r16, r16, rSIZE
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# check reminder
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beq exitsub
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addi r14, r14, -256
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# last block x4
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# init 16 vectors (4 states x4)
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vor v0, v20, v20
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vor v1, v21, v21
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vor v2, v22, v22
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vor v3, v23, v23
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vspltw v4, v17, v0
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vspltw v5, v17, v1
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vspltw v6, v17, v2
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vspltw v7, v17, v3
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vspltw v8, v18, v0
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vspltw v9, v18, v1
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vspltw v10, v18, v2
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vspltw v11, v18, v3
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vor v12, v24, v24
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vspltw v13, v19, v1
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vspltw v14, v19, v2
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vspltw v15, v19, v3
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doubleround # 1
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doubleround # 2
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doubleround # 3
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doubleround # 4
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doubleround # 5
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doubleround # 6
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doubleround # 7
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doubleround # 8
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doubleround # 9
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doubleround # 10
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vadduwm v12, v12, v24
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convert 0
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convert 4
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convert 8
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convert 12
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addition 0
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addition 1
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addition 2
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addition 3
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# store vectors
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stxvw4x vs32, 0, r14
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stxvw4x vs36, r17, r14
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stxvw4x vs40, r18, r14
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stxvw4x vs44, r19, r14
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stxvw4x vs33, r20, r14
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stxvw4x vs37, r21, r14
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stxvw4x vs41, r22, r14
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stxvw4x vs45, r23, r14
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stxvw4x vs34, r24, r14
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stxvw4x vs38, r25, r14
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stxvw4x vs42, r26, r14
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stxvw4x vs46, r27, r14
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stxvw4x vs35, r28, r14
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stxvw4x vs39, r29, r14
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stxvw4x vs43, r30, r14
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stxvw4x vs47, r31, r14
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mtctr r16
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addi rSIZE, r14, -1
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addi rSRC, rSRC, -1
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addi rDST, rDST, -1
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xorlast:
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lbzu r15, 1(rSIZE)
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lbzu r16, 1(rSRC)
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xor r15, r15, r16
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stbu r15, 1(rDST)
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bdnz xorlast
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# zeroing last block
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xxlxor vs0, vs0, vs0
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stxvw4x vs0, 0, r14
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stxvw4x vs0, r17, r14
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stxvw4x vs0, r18, r14
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stxvw4x vs0, r19, r14
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stxvw4x vs0, r20, r14
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stxvw4x vs0, r21, r14
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stxvw4x vs0, r22, r14
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stxvw4x vs0, r23, r14
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stxvw4x vs0, r24, r14
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stxvw4x vs0, r25, r14
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stxvw4x vs0, r26, r14
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stxvw4x vs0, r27, r14
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stxvw4x vs0, r28, r14
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stxvw4x vs0, r29, r14
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stxvw4x vs0, r30, r14
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stxvw4x vs0, r31, r14
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exitsub:
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# zeroing volatile registers
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xxlxor vs0, vs0, vs0
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xxlxor vs1, vs1, vs1
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xxlxor vs2, vs2, vs2
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xxlxor vs3, vs3, vs3
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xxlxor vs4, vs4, vs4
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xxlxor vs5, vs5, vs5
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xxlxor vs6, vs6, vs6
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xxlxor vs7, vs7, vs7
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xxlxor vs8, vs8, vs8
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xxlxor vs9, vs9, vs9
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xxlxor vs10, vs10, vs10
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xxlxor vs11, vs11, vs11
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xxlxor vs12, vs12, vs12
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xxlxor vs13, vs13, vs13
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xxlxor vs32, vs32, vs32
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xxlxor vs33, vs33, vs33
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xxlxor vs34, vs34, vs34
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xxlxor vs35, vs35, vs35
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xxlxor vs36, vs36, vs36
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xxlxor vs37, vs37, vs37
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xxlxor vs38, vs38, vs38
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xxlxor vs39, vs39, vs39
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xxlxor vs40, vs40, vs40
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xxlxor vs41, vs41, vs41
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xxlxor vs42, vs42, vs42
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xxlxor vs43, vs43, vs43
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xxlxor vs44, vs44, vs44
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xxlxor vs45, vs45, vs45
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xxlxor vs46, vs46, vs46
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xxlxor vs47, vs47, vs47
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xxlxor vs48, vs48, vs48
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xxlxor vs49, vs49, vs49
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xxlxor vs50, vs50, vs50
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xxlxor vs51, vs51, vs51
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li rSIZE, 0
|
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li rDST, 0
|
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li rSRC, 0
|
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li rKEY, 0
|
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li rNONCE, 0
|
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li rCNTR, 0
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# epilogue
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addi r14, sp, -160
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li r16, -16
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li r17, -32
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li r18, -48
|
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li r19, -64
|
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li r20, -80
|
|
li r21, -96
|
|
li r22, -112
|
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li r23, -128
|
|
li r24, -144
|
|
li r25, -160
|
|
li r26, -176
|
|
li r27, -192
|
|
li r28, -208
|
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|
|
# load f14, f15
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|
lxvw4x vs14, 0, r14
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|
lxvw4x vs15, r16, r14
|
|
|
|
# load v20 - v31
|
|
lxvw4x vs52, r17, r14
|
|
lxvw4x vs53, r18, r14
|
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lxvw4x vs54, r19, r14
|
|
lxvw4x vs55, r20, r14
|
|
lxvw4x vs56, r21, r14
|
|
lxvw4x vs57, r22, r14
|
|
lxvw4x vs58, r23, r14
|
|
lxvw4x vs59, r24, r14
|
|
lxvw4x vs60, r25, r14
|
|
lxvw4x vs61, r26, r14
|
|
lxvw4x vs62, r27, r14
|
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lxvw4x vs63, r28, r14
|
|
|
|
ld r14, -8(sp)
|
|
ld r15, -16(sp)
|
|
ld r16, -24(sp)
|
|
ld r17, -32(sp)
|
|
ld r18, -40(sp)
|
|
ld r19, -48(sp)
|
|
ld r20, -56(sp)
|
|
ld r21, -64(sp)
|
|
ld r22, -72(sp)
|
|
ld r23, -80(sp)
|
|
ld r24, -88(sp)
|
|
ld r25, -96(sp)
|
|
ld r26, -104(sp)
|
|
ld r27, -112(sp)
|
|
ld r28, -120(sp)
|
|
ld r29, -128(sp)
|
|
ld r30, -136(sp)
|
|
ld r31, -144(sp)
|
|
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blr
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